1. Field of the Invention
Embodiments of the invention relate to a flash memory device and, more particularly, to a programming method adapted for use with a flash memory device.
This application claims priority under 35 U.S.C § 119 to Korean Patent Application 2006-03584 filed on Jan. 12, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
In recent years, volatile and non-volatile memory devices have been incorporated into a host of mobile appliances, such as MP3 players, cellular telephones, portable multimedia players (PMPs), notebook computers, personal digital assistances (PDAs), etc., in ever greater quantities. Emerging mobile appliances require large quantities of digital data storage to support functionality, such as motion picture playback, etc.
Great effort has been expended to meet the demand for ever expanding memory in mobile appliances. One result of this effort is the development of multi-bit memory devices capable of storing greater than a single (1) bit (e.g., a logical “1” or “0”) of data per memory cell. Exemplary multi-bit memory devices are disclosed, for example, in U.S. Pat. No. 6,122,188; U.S. Pat. No. 6,075,734; and U.S. Pat. No. 5,923,587, the subject matter of which is hereby incorporated by reference.
When 1-bit data is stored in a memory cell, the memory cell will exhibit one of two possible threshold voltage distributions, i.e., the memory cell will be programmed (or written) to have one of two data states corresponding to a logical “0” or “1”. Each threshold voltage corresponding to a data state actually appears within an expected voltage distribution—hence the term “threshold voltage distribution”. On the other hand, when 2-bit data is stored in a memory cell, the memory cell will exhibit one of four threshold voltages (i.e., one distribution amongst four possible threshold voltage distributions). These threshold voltages distributions correspond to four (4) logic data states “11”, “10”, “00”, and “01”. Threshold voltage distributions corresponding to four states (ST0, ST1, ST2, and ST3) are illustrated in Figure (FIG.) 1.
Ideally, threshold voltage distributions corresponding to four data states should be carefully controlled such that each threshold voltage distribution exists within a predetermined range or “window.” In order to achieve this goal, one conventional programming method uses an increment step pulse programming (ISPP) scheme. In the ISPP scheme, a threshold voltage shifts by a defined increment of programming voltage in accordance with the repetitive application of one or more programming loops. By setting the programming voltage increment to a small value, threshold voltage distributions may be minutely controlled to secure adequate voltage discrimination margin between respective data states. Unfortunately, the ISSP and similar schemes significantly increase the time required to program a memory cell to a desired data state, particularly for small increment sizes. Accordingly, the size of the program voltage increment will be defined in relation to maximum programming time parameters for a particular memory device.
The application of the ISPP or similar scheme notwithstanding, the corresponding threshold voltage distribution for each data state may be wider than a desired window due to various causes. For example, as indicated by dotted lines 10, 11, 12, and 13 in FIG. 1, respective threshold voltage distributions may expand due to coupling effects between adjacent memory cells during a programming operation. Such a coupling is referred to as “electric field coupling” or “F-poly coupling”.
For example, as illustrated in FIG. 2, assuming that a first memory cell (MCA) and a second memory cell (MCB) are being programmed to have, respectively, any on one of four states, electrical charge accumulates on the floating gate (FG) of memory cell MCB as it is programmed. In turn, a voltage apparent on the floating gate of adjacent memory cell MCA rises due to coupling between the adjacent floating gates of memory cells MCA and MCB. Worse yet, the raised threshold voltage now apparent on the floating gate of memory cell MCA is retained due to the coupling between adjacent floating gates even after programming of memory cell MCB is completed. In this example, memory cell MCB is indicative of memory cells arranged in a wordline direction and/or a bitline direction relative to memory cell MCA.
Due to foregoing coupling effects, the ideal threshold voltages for programmed memory cell MCA expand as indicated by the dotted lines 10, 11, 12, and 12 of FIG. 1. Accordingly, the data state discrimination margin (i.e., the “read margin”) between states is reduced.
One conventional technique adapted to preventing the expansion of threshold voltage distributions due to coupling effects is disclosed, for example, in U.S. Pat. No. 5,867,429, the subject matter of which is hereby incorporated by reference.
In addition to the foregoing electric field and/or F-poly coupling effects, the read margin between memory cell states may be further reduced as memory cell threshold voltages tend to drop over time. This phenomenon has been conventionally examined and is referred to as “hot temperature stress (HTS)”. Under the influence of HTS, charge accumulated on the floating gate of a memory cell drains away into the substrate of the memory device. As accumulated charge on the floating gate is thus reduced, the threshold voltage distributions for the memory cell expand in the direction indicated by dotted lines 20, 21, and 22 of FIG. 3.
Accordingly, the expansion of threshold voltage distributions due to an electric field and/or F-poly coupling effects and HTS present a doubly difficult problem to memory system designers seeking to maintain read margins between memory cell data states. And this problem has only been exacerbated by recent commercial trends toward more complex semiconductor fabricating processes and more densely integrated semiconductor devices.
Accordingly, there exists a requirement to secure additional read margin between memory cell data states (e.g., the corresponding voltage distributions) by controlling for or mitigating the effects of electric field and/or F-poly coupling as well as HTS.